FP8 is All You Need (Part 2): Efficient Ozaki-Bailey Style FFT Through Tensor-core Garner Reformulation and Kulisch Escape Route

The FP64 Squeeze and the Rise of Numerical Alchemy

NVIDIA’s Blackwell Ultra (B300) has made a startling architectural decision: slashing FP64 vector throughput to approximately 1.3 TFLOPS per GPU, a roughly 30-fold reduction compared to its predecessor B200. This move effectively signals that high-precision double-precision floating-point arithmetic is no longer a priority for NVIDIA’s mainstream AI hardware. The new paper on arXiv (2606.23698v1) proposes a clever workaround—using the Ozaki-Bailey framework combined with tensor-core Garner reformulation and a “Kulisch escape route” to recover FP64-equivalent accuracy from FP8 tensor cores.

At its core, this research addresses a fundamental tension: AI workloads thrive on low-precision (FP8, FP16) matrix operations, but scientific computing and certain numerical algorithms still demand double-precision fidelity. The Ozaki Scheme II decomposes high-precision computation into multiple low-precision operations, effectively leveraging the massive throughput of tensor cores (which operate at FP8 speeds) to simulate FP64 results. The “Kulisch escape route” refers to a technique for handling intermediate products without catastrophic rounding errors, while the Garner reformulation optimizes the data flow for modern tensor-core architectures.

Why This Matters

The implications are twofold. First, this work validates that hardware trends are accelerating the divergence between AI-optimized and HPC-optimized silicon. NVIDIA is clearly betting that most customers will accept FP64 emulation via tensor cores rather than demanding dedicated double-precision units. Second, the paper demonstrates that algorithmic innovation can partially compensate for hardware regression—but only for specific workloads like FFTs and linear algebra kernels that are amenable to decomposition.

For AI practitioners, the immediate relevance is indirect but significant. The techniques described could enable more accurate training of models that require numerical stability, such as physics-informed neural networks or scientific ML applications. More broadly, this research signals that the era of “one chip does everything” is ending. AI engineers should expect future hardware to further optimize for low-precision throughput while offloading high-precision tasks to software layers.

Key Takeaways

• NVIDIA’s B300 reduces FP64 throughput by ~30x, making native double-precision impractical for bandwidth-bound workloads and forcing reliance on algorithmic emulation.
• The Ozaki-Bailey framework with tensor-core reformulation can recover FP64-equivalent accuracy from FP8 operations, but only for structured numerical tasks like FFTs.
• AI practitioners should monitor this trend as it may affect workflows requiring numerical precision, particularly in scientific ML and physics-based simulations.
• Hardware specialization is accelerating—future chips will likely continue sacrificing high-precision units in favor of massive low-precision throughput, making software-based precision recovery an essential skill.